Field
The present disclosure relates generally to memory circuitry, and more particularly, to memory control circuitry.
Background
An example static random access memory (SRAM) cell may include a pair of cross-coupled inverters, e.g., each formed from a pair of transistors. The cross coupled inverters may be used to store a bit in one of two stable logic states, e.g., a logic “1” or a logic “0.” Each pair of transistors that may form an inverter may be one P-type metal-oxide-semiconductor (PMOS) transistor and one N-type metal-oxide-semiconductor (NMOS) transistor. By using a combination of a PMOS transistor and an NMOS transistor, static power consumption may be reduced because one of the transistors in each cross-coupled inverter is always off in both logic states.
A “bitcell,” e.g., a single port SRAM cell, may be formed from six transistors. For example, a bitcell may have four transistors, e.g., two each for the pair of cross-coupled inverters. The bitcell may also have two additional transistors. The two additional transistors are used as access transistors. The access transistors may control access to the data in the bitcell during read and write operations. The access transistors may connected to a word line. The word line may be used to enable the access transistors.
Multiport memory cells may provide additional features that may make the operation of the memory cells more flexible. In other words, multiport memory cells may provide more read and write capabilities than a single port SRAM cell. For example, a multiport memory may include additional access transistors. The additional access transistors at each memory cell may provide additional access ports to the memory cell.
In a multi-port memory system, memory port selection information may be latched with pulse latches for every operation cycle. Multi-port memories may use multiple pulse latches to register their respective port selection states. Generally, there may be a variation between each pulse latch due to local environment and layout effects. Layout effects and silicon variations may have significant effects on signal integrity in the latest semiconductor device technologies. The layout effects and silicon variations may be more sensitive at low voltage operation. Variation between pulse latches may cause functional failures, resulting in low yields for multi-port memory systems configured got low voltage operation. Accordingly, minimizing operational variation between pulse latches may be advantageous.